1. Field
Example embodiments relate to a semiconductor memory device. More particularly, example embodiments relate to a NAND flash memory device and a method of programming the same.
2. Description of Related Art
A semiconductor memory device is a kind of a memory device capable of storing data therein as well as reading the stored data. Semiconductor memory devices are largely classified as a random access memory (RAM) or a read only memory (ROM). The RAM is a volatile memory device in which stored data disappears or is lost when there is no power supply and/or power supplied to the RAM is interrupted. The ROM is a non-volatile memory device in which stored data remains and/or is maintained even when there is no power supply and/or power supplied to the ROM is interrupted. Examples of RAM include a dynamic RAM (DRAM), a static RAM (SRAM), etc. Examples of ROM include a programmable ROM (PROM), an erasable PROM (PROM), an electrically EPROM (EEPROM), a flash memory device, etc. Further, flash memory devices may be further classified as a NOR type or a NAND type flash memory device, for example.
Memory cells of a non-volatile memory device respectively have charge storage layers. In general, the charge storage layer employs a floating gate method using a conductor, or a charge trap method using an insulating material. A state in which charges are not stored in a charge storage layer may be referred to as logic 1 and may indicate that no data is stored in the memory cells or that the memory cells have been erased. Also, a state in which charges are stored in a charge storage layer may be referred to as logic 0 and may indicate data is stored in the memory cells or that the memory cells have been programmed.
A program operation is an operation for storing charges in a charge storage layer of a memory cell. However, the charges stored in the charge storage layer through a program operation may be in an unstable state for a time interval or duration following the programming operation. Especially, a flash memory device (e.g., a charge trap flash (CTF) memory device) using charge trap through a charge storage layer requires a time interval or duration until the programmed charges become stable. That is, a threshold voltage of a programmed memory cell may be in an unstable state for a time interval or duration after being programmed. It may take a time interval or duration after being programmed to indicate an accurate level once a threshold voltage of a memory cell becomes stable.
Accordingly, if a verify operation is performed right after a memory cell is programmed, errors may occur due to an unstable threshold voltage. If the threshold voltage is recognized lower than an accurate level, a memory cell that should pass the verifying operation may incorrectly be determined as failing the verifying operation. In this case, the memory cell is excessively programmed. On the contrary, if the threshold voltage is recognized higher than the accurate level, a memory cell that should fail the verifying operation may be incorrectly identified as passing the verifying operation. In this case, the memory cell is less moderately programmed. Therefore, threshold voltage distribution of a memory cell expands.